Parallel Input Serial Output Shift Register Verilog Code
Serial or parallel output. The shift register output mode may be. Module shift (C, SI, PO); input C,SI; output [7:0] PO; reg [7:0]. Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, asynchronous parallel load, serial in, and serial out. For Serial in – parallel out shift registers, all data bits appear on the parallel outputs following the data bits enters sequentially through each flipflop. The following circuit is a four-bit Serial in – parallel out shift register constructed by D flip-flops. VHDL Code for Serial In Parallel Out Shift Register. As you can see I am fairly new to the verilog hdl, I have been trying to create a small functional module using an altera Max7000 series CPLD to take in a 16 bit serial stream and convert it to a 16 bit parallel out. I have checked my input serial stream with a logic analyzer and my data reads.
I am learning and practicing Verilog HDL. I wanted to design a 16 bit parallel in series out shift register.
I wrote this code and tried to simulate it.
simulation_resultI could not understand the reason why data output (dout) signal is always LOW
1 Answer
It works for me.
BUT!
That code can no be turned into gates.You must use 'posedge clk' or 'negedge clk'. Also your load is a-synchronous which is very unusual and cangive race conditions against the clock edge.
Furthermore it is usual to have a reset condition. As long as there is no 'load' signal the dout will produce X-es. This can very much upset the rest of your circuit. Also you have an extra clock delay in dout. You could, if you want, save a clock cycle there. Here its is with an a-synchronous active low reset:
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I wrote a parallel in serial out shift register, which I present here.
The problem I found is that the output for this shift register is always an indetermination as StX, even when I've set assign regout = 0; to be sure. The test is very simple, and everything else is working fine (inreg shifts when shift is enabled, etc).
Am I using the assign in a wrong way? Can anyone point to the problem?
Parallel Input Serial Output Shift Register Verilog Code
1 Answer
The assign is correct.
Since you didn't provide a testbench, my best guess is that you have multiple drivers of regout, most likely when you connected the output port up to something else.
Using this minimal testbench, I see regout change from X to 0, as expected